A High-Speed and Low-Noise Nanopore Amplifier and Event Detector

This thesis focus on the design of an improved-accuracy algorithm for real-time nanopore-based signal detection (e.g. base calling) and high-speed nanopore signal measurement circuits with low-noise. First, the proposed approach is based on the cumulative sum technique but employs a decision-directed policy coupled with a post-decision correction mechanism to achieve at least a 10× accuracy improvement over a previously reported method. As a result the new technique can better accommodate high-speed embedded nanopore measurement applications such as DNA sequencing.

For the circuit design, we apply the CMOS technology since the nanopore-based molecular sensing affords a close coupling between DNA sequencing and semiconductor signal processing. The key analog front-end components of such an ASIC are described herein. In particular, the design of a 3-MHz 130-nm CMOS front-end with reduced area, 2× reduction in power, and 25% noise improvement compare with state of-the-art designs.