An IR-UWB Transmitter IC with Integrated Lossless Neural Data Compression for High-Channel-Count Neural Implants

Abstract

This thesis presents the design, development, and validation of a novel impulse radio ultra-wideband (IR-UWB) transmitter architecture with integrated lossless data compression, targeting high density neural implants. The proposed design incorporates (a) a greatest common divisor (GCD) based compression algorithm that is tailored to the sparse output of a level crossing ADCs (LCADC), (b) an edge combination based UWB transmitter circuit capable of pulse generation for 2-PPM modulation, and (c) programmability to mitigate process, voltage, and temperature (PVT) variations while ensuring spectral compliance. Our results demonstrate the system’s capability to perform real time lossless compression, achieving 50% to ~86% reduction in transmitted bits and up to 94% reduction, leading to significant reductions in transmission energy and enabling scalable channel counts under strict implant power budgets. When combined with the inherent data-rate reduction of LC-ADCs, the overall compression reaches ~259× (corresponding to 99.6% reduction compared to a traditional 10-bit ADC with a 20 kHz sampling rate), enabling proportionally higher channel counts within the same power and bandwidth budget.

The compression algorithm was implemented in System Verilog and synthesized in TSMC 180 nm CMOS, achieving 44.7 µW power consumption and 4114 µm2 area for the compression block (from synthesis results). The transmitter was realized using programmable current-starved inverter delays, glitch generators, and a unit-cell amplifier, co-designed with a circular patch antenna centered at 4 GHz.

Both the digital controller and the transmitter were fabricated using the TSMC 180nm CMOS process. The digital controller and transmitter were tested with a custom receiver architecture.