Implementation of a Neural Network-Based ASIC Chip for Mobile DNA Devices
dc.contributor.advisor | Magierowski, Sebastian | |
dc.contributor.author | Wu, Zhongpan | |
dc.date.accessioned | 2025-04-10T10:57:17Z | |
dc.date.available | 2025-04-10T10:57:17Z | |
dc.date.copyright | 2025-01-14 | |
dc.date.issued | 2025-04-10 | |
dc.date.updated | 2025-04-10T10:57:16Z | |
dc.degree.discipline | Electrical Engineering & Computer Science | |
dc.degree.level | Doctoral | |
dc.degree.name | PhD - Doctor of Philosophy | |
dc.description.abstract | Portable DNA sequencing, particularly using nanopore technology, has the potential to revolutionize genomics by making it accessible in a wide range of environments. However, current state-of-the-art devices face significant challenges due to the lack of integrated bioinformatics processing capabilities. This research addresses these challenges by developing specialized System-on-Chip (SoC) architectures designed for real-time bioinformatics analysis, integrating both a machine learning (ML)-based basecalling accelerator and an Edit Distance (ED) accelerator for sequence comparison. The proposed SoC architecture, based on an open-source RISC-V core, features hardware accelerators tailored for the computational demands of nanopore DNA sequencing. Performance evaluation was conducted in two stages: first through FPGA prototyping, followed by integration into a fabricated SoC. The FPGA prototyping demonstrated nearly 2,000x speedup for ML-based basecalling compared to a standalone RISC-V core, while maintaining an accuracy rate of 83.7%. It also showed an 11.5x and 1.2x energy efficiency improvement over x86 CPUs and high-end GPUs, respectively. The ED accelerator for sequence comparison achieved a 538x boost in energy efficiency compared to commercial CPUs. The fabricated SoC, implemented in a 22-nm CMOS process, successfully demonstrated the feasibility of integrating advanced bioinformatics tasks into a single, power-efficient chip. Evaluation of the fabricated SoC confirmed its capability for real-time, mobile DNA sequencing with high accuracy, reduced power consumption, and significantly improved processing speed, all while reducing dependency on external computational devices. This research represents a significant step towards realizing a fully integrated, stand-alone DNA sequencing solution, capable of performing comprehensive bioinformatics analyses in real time. | |
dc.identifier.uri | https://hdl.handle.net/10315/42870 | |
dc.language | en | |
dc.rights | Author owns copyright, except where explicitly noted. Please contact the author directly with licensing requests. | |
dc.subject.keywords | DNA sequencing | |
dc.subject.keywords | Embedded computing | |
dc.subject.keywords | System-on-chip | |
dc.subject.keywords | Basecalling | |
dc.subject.keywords | Hardware acceleration | |
dc.subject.keywords | Nanopore | |
dc.subject.keywords | Energy-efficiency | |
dc.subject.keywords | FPGA | |
dc.subject.keywords | ASIC | |
dc.subject.keywords | Convolutional neural-network | |
dc.subject.keywords | Machine learning | |
dc.subject.keywords | Portable DNA Devices | |
dc.title | Implementation of a Neural Network-Based ASIC Chip for Mobile DNA Devices | |
dc.type | Electronic Thesis or Dissertation |
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