Design, Fabrication, And Calibration Of A Mems Based Sensing Rosette For Quantifying The Influence Of Strain Engineering On The Piezoresistive Coefficients

Strain has been used extensively in enhancing the electron mobility for high speed and low power transistors. As stretching the silicon atoms away beyond their normal atomic space has a significant influence on the carrier mobility. In this paper, to study the effect of strained silicon on piezoresistivity, the strained silicon will be integrated into a ten element sensing rosette, that utilizes the unique properties of crystalline silicon over the (111) plane to fully extract the six stress components in fully temperature compensated manner. Two chips were designed and fabricated, where the pre-strain state was induced onto the silicon substrate during microfabrication. In the first design, a highly compressive film (stressor layer) was utilized to globally produce a tensile strain at the front side of the substrate where the sensing elements were fabricated. While in the second design, the stressor layer was patterned in a way allowing for inducing both local tensile and compressive transverse uniaxial pre-strain onto the substrate. In another word, stressor strip with intrinsic compressive stress will cause a tensile pre-strain underneath it and compressive stress on both sides. This allows for applying different local strain using the same stressor rather than using nitride capping for tensile or silicon germanium for compressive as used on strained based transistors. To evaluate the effect of the pre-strain on the piezoresistive coefficients, uniaxial, thermal, and hydrostatic loading will be utilized to calibrate both designs.