FPGA-Based Software GNSS Receiver Design for Satellite Applications
Abstract
Global Navigation Satellite System (GNSS) receiver technology has tremendous scope for satellite applications such as radio occultation, precise orbit determination and reflectometry. Spaceborne GNSS receivers are characterised by low power requirements, high processing speed and radiation resistant electronic components. Such sophisticated receivers, also called hardware GNSS receivers, are fabricated for specific applications and hence lack design flexibility. On the other hand, a software GNSS receiver allows easy design modifications without any hardware component replacement. Software receivers employ reconfigurable hardware elements called Field Programmable Gate Arrays (FPGAs).
In this research, a low-power, low-cost software GNSS receiver has been designed and developed using a combination of a microprocessor and FPGA (System-on-Chip or SoC). The developed software GNSS receiver is capable of detecting GPS satellites, tracking them and computing receiver position estimates. Efficient task partitioning is achieved by implementing operations in both, the FPGA and the microprocessor. Also demonstrated is the improvement of processing speed by 20% when certain GNSS receiver operations are performed in the FPGA instead of the microprocessor.
In this research, a low-power, low-cost software GNSS receiver has been designed and developed using a combination of a microprocessor and FPGA (System-on-Chip or SoC). The developed software GNSS receiver is capable of detecting GPS satellites, tracking them and computing receiver position estimates. Efficient task partitioning is achieved by implementing operations in both, the FPGA and the microprocessor. Also demonstrated is the improvement of processing speed by 20% when certain GNSS receiver operations are performed in the FPGA instead of the microprocessor.