Design and Optimization of Sensor Interface Circuitry and All-Digital PLL in 22nm Technology with gm/ID Methodology Using Precalculated Look-Up Tables.

Abstract

This thesis presents the design of a monolithic System-on-Chip (SoC) front-end for solid-state nanopore DNA sequencing, implemented in GlobalFoundries 22nm FD-SOI technology. A major bottleneck in portable sequencing is the massive parasitic capacitance of the sensor (approx. 5 pF), which severely limits the bandwidth required to detect rapid, picoampere-level ion currents. Additionally, designing high-performance analog interfaces in deep-submicron nodes using traditional, iterative SPICE simulations is highly inefficient. To address these challenges, this research establishes a systematic, hierarchical "Inverse Design" framework based on the gm/ID methodology. By utilizing 4D Look-Up Tables (LUTs) extracted from BSIM-IMG compact models, this flow deterministically synthesizes transistor geometries directly from system-level specifications. Crucially, the methodology integrates back-gate biasing (FBB) as a fourth design dimension to dynamically trade off leakage for speed and maximize voltage headroom. Utilizing this synthesis flow, a Transimpedance Amplifier (TIA) was designed, achieving a 1 MHz bandwidth and a 5 Mohms transimpedance gain while driving the large capacitive sensor load. To provide the low-jitter timing infrastructure required for full system integration and precise ADC sampling, a wide-range All-Digital Phase-Locked Loop (ADPLL) featuring a MASH 1-1-1 Sigma-Delta Modulator was also implemented, achieving a phase noise of -84 dBc/Hz at a 1 MHz offset. Ultimately, this work demonstrates that a deterministic LUT-based synthesis approach successfully enables robust, high-performance mixed-signal IC design for biosensors while eliminating the reliance on trial-and-error manual sizing.