A Scalable Hardware-Efficient CSNN Accelerator with Binarized STDP and STDG-based Hybrid Learning
| dc.contributor.advisor | Amirsoleimani, Amirali | |
| dc.contributor.author | Rahimian Kalatehbali, Hamid | |
| dc.date.accessioned | 2026-07-24T15:31:41Z | |
| dc.date.available | 2026-07-24T15:31:41Z | |
| dc.date.copyright | 2025-07-31 | |
| dc.date.issued | 2026-07-24 | |
| dc.date.updated | 2026-07-24T15:31:40Z | |
| dc.degree.discipline | Electrical and Computer Engineering | |
| dc.degree.level | Master's | |
| dc.degree.name | MASc - Master of Applied Science | |
| dc.description.abstract | Spiking neural networks (SNNs) offer a biologically inspired, energy-efficient computing paradigm that processes information through sparse, event-driven spike signals. In this work, we present Binarized spike-timing dependent plasticity-gradient (BSTDPG), a novel SNN framework that combines Time-to-first-spike (TTFS) latency encoding with simple integrate-and-fire (IF) neuron model, binarized convolutional layers with local Spike-timing dependent plasticity (STDP) learning rule, and a gradient-based classifier. To support hybrid learning, the final output layer is trained using either a Support Vector Machine (SVM) or gradient-based backpropagation, allowing flexible deployment in both unsupervised and supervised settings. The proposed architecture consists of two spiking convolutional layers followed by maxpooling and a classifier. A key innovation is the zero-skip optimization technique, which dynamically prunes inactive spike regions based on bounding boxes generated from TTFS-encoded spike trains. This drastically reduces unnecessary computations during training and inference. For instance, processing sample digit '0' during its first timestep without optimization results in full 28 × 28 convolution and 7860 ns latency. With zero-skip enabled, the latency drops to 1710 ns, achieving a 4.6× speedup and 78.2% processing time reduction. A similar improvement is observed at the full network level, where zero-skip reduces prediction latency from 1459 µs to 1212 µs, saving 246 µs. We evaluate BSTDPG on Modified National Institute of Standards and Technology database (MNIST) and Fashion-MNIST (F-MNIST) across both shallow and deep network configurations. The model achieves accuracies of 99.1% and 91.0%, respectively, outperforming or matching several state-of-the-art SNNs such as BANN, BS4NN, S4NN, and even deep temporal SNNs, despite using fewer layers. Together, these innovations highlight BSTDPG as a promising architecture for low-latency, low-power neuromorphic applications including edge-AI, robotics, and event-based vision, offering an effective trade-off between biological plausibility, efficiency, and learning performance. | |
| dc.identifier.uri | https://hdl.handle.net/10315/43836 | |
| dc.language | en | |
| dc.rights | Author owns copyright, except where explicitly noted. Please contact the author directly with licensing requests. | |
| dc.subject | Computer engineering | |
| dc.subject | Electrical engineering | |
| dc.subject | Neurosciences | |
| dc.subject.keywords | Sparse Computation | |
| dc.subject.keywords | Hardware Accelerator | |
| dc.subject.keywords | Image Classification | |
| dc.subject.keywords | Convolutional Spiking Neural Network | |
| dc.subject.keywords | Neuromorphic | |
| dc.title | A Scalable Hardware-Efficient CSNN Accelerator with Binarized STDP and STDG-based Hybrid Learning | |
| dc.type | Electronic Thesis or Dissertation |
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